Developed in partnership with the world's leading chip companies over a 12 year period, FreeRTOS is the market leading real time operating system (or RTOS), and the de-facto standard solution for microcontrollers and small microprocessors.

With millions of deployments in all market sectors, blue chip companies trust FreeRTOS because it is professionally developed, strictly quality controlled, robust, supported, free to use in commercial products without a requirement to expose proprietary source code, and has no IP infringement risk.

Welcome. The purpose of this site is to share the lore of designing parallel computers and integrated systems-on-chips using FPGAs (field-programmable gate arrays). It is the continuation of the long fallow FPGA CPU News.

All content is written/edited by Jan Gray, President of Gray Research LLC.

All content is Copyright © 2000-2016, Gray Research LLC. All rights reserved.

RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

An OS to build, deploy and securely manage billions of devices

Pydgin provides a collection of classes and functions which act as an embedded architectural description language (embedded-ADL) for concisely describing the behavior of instruction set simulators (ISS). An ISS described in Pydgin can be directly executed in a Python interpreter for rapid prototyping and debugging, or alternatively can be used to automatically generate a performant, JIT-optimizing C executable more suitable for application development.

Automatic generation of JIT-enabled ISS from Pydgin is enabled by the RPython Translation Toolchain, an open-source tool used by developers of the PyPy JIT-optimizing Python interpreter.

An ISS described in Pydgin implements an interpretive simulator which can be directly executed in a Python interpreter for rapid prototyping and debugging. However, Pydgin ISS can also be automatically translated into a C executable implementing a JIT-enabled interpretive simulator, providing a high-performance implementation suitable for application development. Generated Pydgin executables provide significant performance benefits in two ways. First, the compiled C implementation enables much more efficient execution of instruction-by-instruction interpretive simulation than the original Python implementation. Second, the generated executable provides a trace-JIT to dynamically compile frequently interpreted hot loops into optimized assembly.

The content contained herein is correct as of January 2017, and represents the status quo as of the time it was written. Google’s security policies and systems may change going forward, as we continually improve protection for our customers.

Seit dem Jahr 2000 bietet GILLES.TOOLING Motorradbegeisterten
in aller Welt innovative und hochwertige Zubehörteile an.

Firmengründer Gerhard Gilles vereint als ehemaliger Motorradrennfahrer
die Leidenschaft für diesen Sport mit dem technischen Wissen eines
erfahrenen CNC-Fräsers: aus der Entwicklung der ersten multivariablen
Fussrastenanlage AS31GT ist ein dynamisches Unternehmen entstanden,
welches heute seine erweiterte Produktpalette weltweit vertreibt.

EnhanceIO driver is based on EnhanceIO SSD caching software product
developed by STEC Inc. EnhanceIO was derived from Facebook's open source
Flashcache project. EnhanceIO uses SSDs as cache devices for
traditional rotating hard disk drives (referred to as source volumes
throughout this document).

EnhanceIO can work with any block device, be it an entire physical
disk, an individual disk partition,  a RAIDed DAS device, a SAN volume,
a device mapper volume or a software RAID (md) device.

The source volume to SSD mapping is a set-associative mapping based on
the source volume sector number with a default set size
(aka associativity) of 512 blocks and a default block size of 4 KB.
Partial cache blocks are not used. The default value of 4 KB is chosen
because it is the common I/O block size of most storage systems.  With
these default values, each cache set is 2 MB (512 * 4 KB).  Therefore,
a 400 GB SSD will have a little less than 200,000 cache sets because a
little space is used for storing the meta data on the SSD.

EnhanceIO supports three caching modes: read-only, write-through, and
write-back and three cache replacement policies: random, FIFO, and LRU.

Read-only caching mode causes EnhanceIO to direct write IO requests only
to HDD. Read IO requests are issued to HDD and the data read from HDD is
stored on SSD. Subsequent Read requests for the same blocks are carried
out from SSD, thus reducing their latency by a substantial amount. 

In Write-through mode - reads are handled similar to Read-only mode.
Write-through mode causes EnhanceIO to write application data to both
HDD and SSD. Subsequent reads of the same data benefit because they can
be served from SSD.

Write-back improves write latency by writing application requested data
only to SSD. This data, referred to as dirty data, is copied later to
HDD asynchronously. Reads are handled similar to Read-only and
Write-through modes.

I've published a new HOWTO on my website:

Enrico already wrote about the Why (and the What, Who and When), so I'll just quote his conclusion and move on to the How.

I now have an XMPP setup which has all the features of the recent fancy chat systems, and on top of that it runs, client and server, on Free Software, which can be audited, it is federated and I can self-host my own server in my own VPS if I want to, with packages supported in Debian.