This page describes Pressure Stall Information (PSI), how to use it, tools and components that work with PSI, and some case studies showing how PSI is used in production today for resource control in large data centers.
Overview

PSI provides for the first time a canonical way to see resource pressure increases as they develop, with new pressure metrics for three major resources—memory, CPU, and IO.

These pressure metrics, in conjunction with cgroup2 and other kernel and userspace tools described below, allow you to detect resource shortages while they’re developing, and respond intelligently—by pausing or killing non-essentials, reallocating memory in the system, load shedding, or other actions.

PSI stats are like barometers that provide fair warning of impending resource shortages, enabling you to take more proactive, granular, and nuanced steps when resources start becoming scarce.

See the PSI git repo for additional information.

A cross-platform C library to retrieve CPU features (such as available instructions) at runtime

Welcome. The purpose of this site is to share the lore of designing parallel computers and integrated systems-on-chips using FPGAs (field-programmable gate arrays). It is the continuation of the long fallow FPGA CPU News.

All content is written/edited by Jan Gray, President of Gray Research LLC.

All content is Copyright © 2000-2016, Gray Research LLC. All rights reserved.

RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

Pydgin provides a collection of classes and functions which act as an embedded architectural description language (embedded-ADL) for concisely describing the behavior of instruction set simulators (ISS). An ISS described in Pydgin can be directly executed in a Python interpreter for rapid prototyping and debugging, or alternatively can be used to automatically generate a performant, JIT-optimizing C executable more suitable for application development.

Automatic generation of JIT-enabled ISS from Pydgin is enabled by the RPython Translation Toolchain, an open-source tool used by developers of the PyPy JIT-optimizing Python interpreter.

An ISS described in Pydgin implements an interpretive simulator which can be directly executed in a Python interpreter for rapid prototyping and debugging. However, Pydgin ISS can also be automatically translated into a C executable implementing a JIT-enabled interpretive simulator, providing a high-performance implementation suitable for application development. Generated Pydgin executables provide significant performance benefits in two ways. First, the compiled C implementation enables much more efficient execution of instruction-by-instruction interpretive simulation than the original Python implementation. Second, the generated executable provides a trace-JIT to dynamically compile frequently interpreted hot loops into optimized assembly.

This article presents architecture and implementation of the
b16 stack processor. This processor is inspired by Chuck
Moore’s newest Forth processors. The minimalistic design
fits into small FPGAs and ASICs and is ideally suited for
applications that need both control and calculations. The
synthesizible implementation uses Verilog.

Sie können CPU-Ressourcen hinzufügen, ändern oder konfigurieren, um die Leistung einer virtuellen Maschine zu verbessern. Sie können die meisten der CPU-Parameter beim Erstellen virtueller Maschinen oder nach der Installation des Gastbetriebssystems festlegen. Bei einigen Aktionen ist es erforderlich, die virtuelle Maschine auszuschalten, bevor Sie die Einstellungen ändern.