Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.
Hardware construction language (not C to Gates)
Embedded in the Scala programming language
Algebraic construction and wiring
Abstract data types and interfaces
Bulk connections
Hierarchical + object oriented + functional construction
Highly parameterizable using metaprogramming in Scala
Supports layering of domain specific languages
Sizeable standard library including floating-point units
Multiple clock domains
Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools
Open source on github with modified BSD license
Complete set of docs
Growing community of adoptersWelcome. The purpose of this site is to share the lore of designing parallel computers and integrated systems-on-chips using FPGAs (field-programmable gate arrays). It is the continuation of the long fallow FPGA CPU News.
All content is written/edited by Jan Gray, President of Gray Research LLC.
All content is Copyright © 2000-2016, Gray Research LLC. All rights reserved.
Learn about FPGAs, Verilog, and VHDL. Tutorials for beginners to help you get started in the wonderful world of FPGAs.
There is now a complete Open Source tool chain for some FPGAs from Lattice Semiconductor. For a convincing video that these devices and the Open Source development tools are useful, see:
Introduction to the Open Source FPGA toolchain short or long@32c3 by Clifford Wolf
Forth on icestick by James Bowman15478282925_5accdb9d95_o
The Parallella Board
• 18-core credit card sized computer
• Includes Xilinx Zynq SOC (FPGA+ Dual core ARM A9)
• Gigabit Ethernet
• 1GB SDRAM
• Micro-SD storage
• Up to 48 GPIO pins
• HDMI, USB (optional)
• Open source design files
• #1 in energy efficiency
• Runs Linux
• Starting at $99
This article presents architecture and implementation of the
b16 stack processor. This processor is inspired by Chuck
Moore’s newest Forth processors. The minimalistic design
fits into small FPGAs and ASICs and is ideally suited for
applications that need both control and calculations. The
synthesizible implementation uses Verilog.
- Cyclone V GX 5CGXFC5C6F27C7N Device
- LPDDR2, SRAM, FLASH EPCQ256
- Arduino Header, 2x20 GPIO Header, HSMC, UART to USB, HSMC, HDMI TX