There’s been some exciting news about RISC-V microcontrollers recently with Gigadevice announcing GD32V, one of the first RISC-V general-purpose microcontrollers, which outperforms its Arm Cortex-M3 equivalent in terms of performance and power consumption.

The company also announced some development boards, but they are not quite that easy to purchase being listed on Tmall website in China. The good news is that Sipeed has introduced Longan Nano development board powered by GD32VF103CBT6 microcontroller, and it’s up for sale on Seeed Studio for $4.9.

The HiFive1 is an Arduino-compatible development kit featuring the Freedom E310, the industry’s first commercially available RISC-V SoC.
Freedom Everywhere

The Freedom E310 (FE310) is the first member of the Freedom Everywhere family of customizable SoCs. Designed for microcontroller, embedded, IoT, and wearable applications, the FE310 features SiFive’s E31 CPU Coreplex, a high-performance, 32-bit RV32IMAC core. Running at 320+ MHz, the FE310 is among the fastest microcontrollers in the market.

Additional features include a 16KB L1 Instruction Cache, a 16KB Data SRAM scratchpad, hardware multiply/divide, a debug module, flexible clock generation with on-chip oscillators and PLLs, and a wide variety of peripherals including UARTs, QSPI, PWMs, and timers. Multiple power domains and a low-power standby mode ensure a wide variety of applications can benefit from the FE310.

HiFive1
A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

The HiFive1 is an Arduino-Compatible development kit featuring the Freedom E310, the industry’s first commercially available RISC-V SoC.

RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

An OS to build, deploy and securely manage billions of devices

Pydgin provides a collection of classes and functions which act as an embedded architectural description language (embedded-ADL) for concisely describing the behavior of instruction set simulators (ISS). An ISS described in Pydgin can be directly executed in a Python interpreter for rapid prototyping and debugging, or alternatively can be used to automatically generate a performant, JIT-optimizing C executable more suitable for application development.

Automatic generation of JIT-enabled ISS from Pydgin is enabled by the RPython Translation Toolchain, an open-source tool used by developers of the PyPy JIT-optimizing Python interpreter.

An ISS described in Pydgin implements an interpretive simulator which can be directly executed in a Python interpreter for rapid prototyping and debugging. However, Pydgin ISS can also be automatically translated into a C executable implementing a JIT-enabled interpretive simulator, providing a high-performance implementation suitable for application development. Generated Pydgin executables provide significant performance benefits in two ways. First, the compiled C implementation enables much more efficient execution of instruction-by-instruction interpretive simulation than the original Python implementation. Second, the generated executable provides a trace-JIT to dynamically compile frequently interpreted hot loops into optimized assembly.